Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes

Modular design of totally self-checking checkers for 1-out-of-n codes

High-Speed and Low-Power Flash ADCs Encoder

This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-i...

A Pragmatic Approach to On-Line Testing

Modeling and simulation of time domain faults in digital systems p. 5 Sizing CMOS circuits for increased transient error tolerance p. 11 Low-area on-chip circuit for jitter measurement in a phase-locked loop p. 17 Necessary and sufficient conditions for the existence of totally self-checking circuits p. 25 Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circ...

Design Automation of Fpga Based Reliable Checkers

This work presents a CAD tool incorporating several approaches to the design of reliable checkers for totally self checking control units. Some of the approaches are original. To achieve the required properties, unidirectional error detecting codes are applied to the outputs of the control units. Traditionally, minimum check bits in the code serves as the criterion for its selection. The new pr...

Novel Single and Double Output TSC Berger Code Checkers

This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor stuckon, resistive bridging faults and breaks. A benefit of the proposed type-I single and double output checkers is that all faults are testable by a very small set of code words t...